Many complex electrical systems commonly employ multiple buffers for processing, usually first-in, first-out (FIFO) buffers, to store data transferred between operations especially when transferring data between synchronous but not synphase clock domains. When operating in accordance with a standard, such as a serializer-deserilizer (SerDes) standard, such FIFOs might be required to provide information under very precisely timed read and write operations. However, due to variations in processing, circuit layout, and other considerations alignment of pointers presents a design challenge, especially at high speed operation. This limits FIFO buffer usage in designs where multiple FIFOs need to be aligned for specific standard requirements. Normally, FIFO pointer resets are synchronized to the write/read clock domain, which synchronization introduces uncertainty to the pointer alignment between different FIFO buffers. Known existing solutions daisy chain the FIFO control signals (in master-slave configuration) to align pointers. However, performance of these techniques degrades in high speed applications.